Publications

    Conferences Papers

    • A Storage-Effective BTB Organization for Servers.
      Truls Asheim, Boris Grot, and Rakesh Kumar. In 29th International Symposium on High Performance Computer Architecture (HPCA), February, 2023.

    • A Specialized BTB Organization for Servers.
      Truls Asheim, Boris Grot, and Rakesh Kumar. In 31st International Conference on Parallel Architectures and Compilation Techniques (PACT), October, 2022. (Short paper/Extended Abstract)

    • Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control.
      Odin Ugedal and Rakesh Kumar. In 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), November, 2022.

    • Twig: Profile-Guided BTB Prefetching for Data Center Applications.
      Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K Soundararajan, Rakesh Kumar, Joseph Devietti, Sreenivas Subramoney, Gilles A Pokam, Heiner Litz, and Baris Kasikci. In 54th International Symposium on Microarchitecture (MICRO), October, 2021.

    • Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors.
      Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer. In 26th International Symposium on High Performance Computer Architecture (HPCA), February, 2020.

    • Freeway: Maximizing MLP for Slice-Out-of-Order Execution.
      Rakesh Kumar, Mehdi Alipour, David Black-Schaffer. In 25th International Symposium on High Performance Computer Architecture (HPCA), February, 2019.

    • FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors.
      Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer. In Design, Automation and Test in Europe Conference and Exhibition (DATE) March, 2019.

    • Blasting Through The Front-End Bottleneck With Shotgun. (Video)
      Rakesh Kumar, Boris Grot, Vijay Nagarajan. In 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) March, 2018.

    • HW/SW Co-designed Processors: Challenges, Design Choices and a Simulation Infrastructure for Evaluation.
      Rakesh Kumar, José Cano Reyes, Aleksandar Brankovic, Demos Pavlou, kyriakos Stavrou, Enric Gibert, Alejandro Martínez, and Antonio González. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) April, 2017.

    • Boomerang: a Metadata-Free Architecture for Control Flow Delivery. (Video)
      Rakesh Kumar, Cheng-Chieh Huang, Boris Grot, Vijay Nagarajan. In 23rd International Symposium on High Performance Computer Architecture (HPCA), February, 2017.

    • C3D: Mitigating the NUMA Bottleneck via Coherent DRAM Caches.
      Cheng-Chieh Huang, Rakesh Kumar, Marco Elver, Boris Grot, Vijay Nagarajan. In 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October, 2016.

    • Quantitative Characterization of the Software Layer of a HW/SW Co-Designed Processor.
      Jose Cano, Rakesh Kumar, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, and Antonio González. In International Symposium on Workload Characterization (IISWC), September 2016.

    • Speculative Dynamic Vectorization to Assist Static Vectorization in a HW/SW Co-designed Environment.
      Rakesh Kumar, Alejandro Martínez, and Antonio González. In 20th IEEE/ACM International Conference on High Performance Computing (HiPC) December, 2013.

    • Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment.
      Rakesh Kumar, Alejandro Martínez, and Antonio González. In 15th IEEE International Conference on High Performance Computing and Communications (HPCC) November, 2013.

    • Dynamic Selective Devectorization for Efficient Power Gating of SIMD units in a HW/SW Co-designed Environment.
      Rakesh Kumar, Alejandro Martínez, and Antonio González. In 25th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) October, 2013.

    • Speculative Dynamic Vectorization for HW/SW Co-designed Processors.
      Rakesh Kumar, Alejandro Martínez, and Antonio González. In 21st IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT) September 2012. (Short paper)

    Journal Articles

    • Shooting Down The Server Front-End Bottleneck.
      Rakesh Kumar and Boris Grot. In ACM Transactions on Computer Systems (ACM TOCS), Volume 38, No 3-4, 2022.

    • Dependence Aware Slice Execution to Boost MLP in Slice-Out-of-Order Cores.
      Rakesh Kumar, Mehdi Alipour, David Black-Schaffer. To appear in ACM Transactions on Architecture and Code Optimizations (ACM TACO), 2022.

    • BTB-X: A Storage-Effective BTB Organization.
      Truls Asheim, Boris Grot, and Rakesh Kumar. In IEEE Computer Architecture Letters (IEEE CAL), 2021.

    • Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in a HW/SW Co-designed Environment.
      Rakesh Kumar, Alejandro Martínez, and Antonio González. In ACM Transactions on Computer Systems (ACM TOCS), 2016.

    • Efficient Power Gating of SIMD Accelerators through Dynamic Selective Devectorization in a HW/SW Co-designed Environment.
      Rakesh Kumar, Alejandro Martínez, and Antonio González. In ACM Transactions on Architecture and Code Optimizations (ACM TACO), 2014.

    Workshop Papers

    • Impact of Microarchitectural State Reuse on Serverless Functions.
      Truls Asheim, Tanvir Ahmed Khan, Baris Kasikci, and Rakesh Kumar. In 8th International Workshop on Serverless Computing (WoSC), November, 2022.

    • Uncovering Hidden Instructions in Armv8-A Implementations.
      Fredrik Strupe, Rakesh Kumar. In 9th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP), October, 2020.

    • Minimum Out-of-Order Core.
      Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer. In Student Research Competition held at 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October, 2018. [2nd best student poster]

    • DARCO: Infrastructure for Research on HW/SW co-designed Virtual Machines.
      D. Pavlou, A. Brankovic, R. Kumar, M. Gregori, K. Stavrou, E. Gibert, A. Gonzalez. In 4th Workshop on Architectural and Microarchitectural Support for Binary Translation AMAS-BT'11, held in conjuction with the 38th International Symposium on Computer Architecture ISCA 2011, June, 2011.

    • Adaptive Block Pinning for Multi-core Architectures.
      Rakesh Kumar, Nitin Chaturvedi, and TSB Sudarshan. In the web proceedings of 15th International Conference on High Performance Computing, student symposium HiPC-SS08, Dec 2008. [Best Presentation Award]

    Other Publications

    • Speculative Dynamic Vectorization to Assist Static Vectorization in a HW/SW Co-designed Environment.
      Rakesh Kumar, Alejandro Martínez, and Antonio González. In Hipeac Compiler, Architecture and Tools Conference at Haifa, Israel, November, 2013.

    • Modelling HW/SW Co-Designed Processors.
      J. Cano, A. Brankovic, R. Kumar, D. Zivanovic, D. Pavlou, K. Stavrou, E. Gibert, A. Martínez, G. Dot, F. Latorre, A. Barceló, and A. González. In Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems ACACES 2012, Fiuggi, Italy, July 2012.

    • Non Inclusion Property in Multi Core Architectures with Multi-level Caches
      Rakesh Kumar, Nitin Chaturvedi, and TSB Sudarshan. In National Conference on High Computing Technologies, Nov 2008, Rajkot, India. [Best Paper Award]

    Thesis

    • Optimizing SIMD Execution in HW/SW Co-designed Processors.
      Rakesh Kumar. Universitat Politècnica de Catalunya, Spain. July 2014.

▲ Top