I am an Associate Professor in the Department of Computer Science at Norwegian University of Science and Technology (NTNU). I am affiliated with Computer Architecture Lab (CAL) in the Computing Unit. Before joining NTNU, I was a post-doctoral researcher at Uppsala University, Sweden and the University of Edinburgh, UK. I received my PhD from UPC, Barcelona in 2014. My current research focuses on improving the efficiency of large-scale datacenters through improvement in processor microarchitecture and memory systems. My previous work explored hardware/software co-designed processors (think of Nvidia Denver) as an energy-efficient alternative to conventional (hardware only) processors. I have also investigated dynamic code translation and optimizations, especially vectorization.
Doctor of Philosophy, Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain. July 2014.
Thesis : Optimizing SIMD Execution in HW/SW Co-designed Processors.
Advisors : Dr. Alejandro Martínez and Prof. Antonio González.
Master of Engineering, Microelectronics, Birla Institute of Technology and Science (BITS) Pilani , India. Dec 2008.
Thesis : Cache Design issues for Multi-core Architectures.
Advisor : Prof. TSB Sudarshan.
Bachelor of Technology, Electronics and Communications Engineering, Kurukshetra University, India. July 2005.
Marks : 75.4%.
Program Committee: HPCA(2023, 2022), YArch@ASPLOS(2022), IPDPS(2019), ICPP(2017), MCC(2017)
External Review Committee: MICRO (2022), ISCA(2021, 2020), HPCA(2019)
Tutorial Review Committee: SC (2022)
Reviewer (Not PC/ERC): MICRO(2019), HPCA(2017, 2016, 2013), SC(2016), CGO(2016), ASPLOS(2015), ISCA(2015), NAS(2015)
Journal Review: IEEE Transactions on Computers, ACM Transactions on Computer Systems, IEEE Computer Architecture Letters, Elsevier Microprocessors and Microsystems, Technical Gazette
Co-developer of DARCO, an infrastructure for research on HW/SW co-designed Virtual Machines.