Design of PID Controller Cascaded with Filter for First Order Time Delay Process

Systematic methods and tools for managing the complexity

Process Control (T4-8P)

Dr M. Shamsuzzoha
Yeungnam University
Process System Design & Control Lab, school of chemical engineering
Address for correspondence:
Process System Design & Control Lab, Room No-401 School of Chemical Engineering and Technology, Yeungnam University214-1 Dae-Dong Kyongsan Kyongbuk 712-749 SOUTH KOREA, Phone No: +82-53-810-3241, Fax:+82-53-811-3262
Korea, Republic of

Keywords: PID Controller Tuning, First Order Plus Dead Time Process, Disturbance Rejection, First Order Lead/Lag, Filter, Two-Degree-of-Freedom Controller

Design of PID Controller Cascaded with Filter for First Order Time Delay Process
M. Shamsuzzoha, Moonyong Lee
School of Chemical Engineering and Technology, Yeungnam University,
Kyongsan, 712-749, Korea

Abstract

The majority of controllers used in the process industries are still proportional, integral, and derivative (PID). There are many reasons for this, including the fact that they are well understood by many industrial operational, technical, and maintenance individuals, and, in many applications, the fact that a properly designed and well-tuned PID controller meets or exceeds the control objectives. Although advance control techniques such as model predictive control can provide significant improvements, a PID controller that is properly designed and tuned has proved to be satisfactory for the vast majority of industrial control loop.
The well-known internal model control (IMC) PID rules have the advantage that a clear tradeoff between closed-loop performance and robustness to model inaccuracies is achieved with a single tuning parameter. The reported literatures show that IMC-PID provides good setpoint tracking but very sluggish disturbance response for tuning the process with a small time-delay/time-constant ratio. However, for many process control applications, disturbance rejection is much more important than setpoint tracking. Therefore, controller design that emphasizes disturbance rejection rather than setpoint tracking, is an important design problem that has received renewed interest recently.
Recently Skogestad, (2003) proposed a rule for modification of the integral terms to improve disturbance rejection for integrating processes and also proposed the simple analytical rules for the model reduction to obtain a model in this form. Chen and Seborg, (2002) proposed a design method for PID controllers based on the direct synthesis approach. Some of the workers (Lee et al. 1998; and Horn et al. 1996) proposed the same kind of lead lag filter to resolve this problem, but still it has lack of consistency in result.
Therefore, in this article, we have proposed an analytical tuning method for the PID controller cascaded with a lead/lag filter for the FOPDT process based on the IMC design principle. The controller is designed for the disturbance rejection and two-degree-of-freedom control structure is used to slacken the overshoot in the set-point response. The simulation study shows that the proposed design method provides better disturbance rejection than the conventional PID design methods when the controllers are tuned to have the same degree of robustness by the measure of maximum sensitivity (Ms). A single tuning parameter closed-loop time constant (λ) guideline is provided for several different robustness levels.

Keywords: PID Controller Tuning, First Order Plus Dead Time Process, Disturbance Rejection, First Order Lead/Lag, Filter, Two-Degree-of-Freedom Controller

Presented Tuesday 18, 13:30 to 15:00, in session Process Control (T4-8P).