The advantages of MPC, compared to other control algorithms, have been capitalized upon in the chemical-process industry over the last three decades. MPC is an attractive algorithm for a wide range of control problems, due to its ability to handle Multiple-Input-Multiple-Output systems and its explicit incorporation of constraints. However, each control decision of MPC in based on the solution of an optimization problem, which makes it a computationally expensive algorithm for applications of small physical size, where the computational power that can be employed is limited.

Recently there has been an increased interest for Systems on a Chip (SoC) that can solve an MPC problem efficiently, while occupying small area and demonstrating low power consumption [1, 2, 3]. In such systems, the precision used for the arithmetic operations is a decisive factor, since the smaller the wordlength of an arithmetic unit, the smaller the area it occupies, and the smaller its power consumption. The reduced precision, though, can lead to poor control performance or even instability.

In this work we study the connection between the performance of a hardware architecture implementing an embedded MPC algorithm and the wordlength used. In [4] it was shown that by using the Logarithmic Number System (LNS) it is possible to reduce the wordlength of the arithmetic unit to 16 bits (compared to a 64-bit Floating Point) for a particular control problem. Extending this work, further reduction in the wordlength is sought using Monte Carlo LNS (MCLNS) arithmetic.

Parker [5] introduced Monte-Carlo Floating Point (MCFP) in contrast to deterministic floating point. MCLNS, like deterministic LNS, stores a specific number of precision bits. When the result of an arithmetic operation is approximate, due to rounding or truncation, the unknown bits are assumed to be zero. In MCLNS we assume the infinite set of truncated bits form an unbiased random value, rather than being zero. Some initial results have shown that, for some algorithms, the introduced randomization results in the mutual cancellation of error coming from repetitive arithmetic operations producing a usable MCLNS result with fewer bits than is possible with deterministic LNS. This allows for the reduction of the MCLNS wordlength.

The outcomes of the simulation study of MCLNS are transferred into hardware in order to mirror the reduction in the occupied area resulting from the reduced wordlength. The functionality of the resulting architecture is verified by hardware-in-the-loop simulation, and a comparison with other proposed architectures for embedded MPC is presented.

[1] P. Vouzis, L. Bleris, M. Kothare, M. Arnold, “A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control,” Submitted to IEEE Transactions on Control Systems Technology (2006).

[2] M. H. He and K. V. Ling, “Model Predictive Control on a Chip,” in The 5th Internation Conference on Control and Automation, (Hungary, Budapest), pp. 528–531, June 26–29 2005.

[3] T. A. Johansen, W. Jackson, R. Schreiber, and P. Tøndel, “Hardware Architecture Design for Explicit Model Predictive Control,” In proceedings of the Americal Control Conference, (Minneapolis, MN), 14–16 June 2006.

[4] L. G. Bleris, J. G. Garcia, M. V. Kothare, and M. G. Arnold, “Towards Embedded Model Predictive Control for System-on-a-Chip Applications,” Journal of Process Control, vol. 16, pp. 255–264, March 2006.

[5] S. Parker, B. Pierce, P. Eggert, “Monte Carlo Arithmetic: How to Gamble with Floating Point and Win,” Computing in Science & Engineering, Vol. 2, No. 4, pp. 58–68, July/August 2000.