Growth of semiconducting nanoparticle arrays by chemical or physical deposition has been demonstrated on semiconductor and dielectric surfaces. Chemical vapor deposition (CVD) is a well characterized process in the semiconductor industry; however, size dispersity and random nanoparticle location present challenges in exploiting these growth methods as technological applications rely on the discreteness of size, such as quantum confinement effects, and precise positioning for addressability. Various patterning schemes have been advanced for heteroepitaxial growth on semiconductor substrates that manipulate the strain in the semiconductor substrate to direct nanoparticle positioning. In contrast to Stransky-Krastanov growth observed on crystalline semiconductor substrates, Volmer-Weber three-dimensional island growth occurs on amorphous dielectrics producing random arrays of semiconducting nanoparticles with wide size distributions. Disordered nanoparticle arrays result from the random nature of adatom diffusion on the insulator surface before forming a critical cluster at randomly located nucleation sites. The problem of polydisperse nanoparticle size can be somewhat suppressed by using a two-step approach separating nucleation and growth; however, randomness in deposition location still persists. The key to controlling nucleation and growth is to manage the density of adatoms on the surface. Despite the great number of potential technologies for semiconductor nanoparticles on amorphous insulator substrates, methods to controllably organize nanoparticles on amorphous substrates are lacking and this is particularly true at CVD growth temperatures.

We report on the bottom-up assembly of Si and Ge nanoparticles into top-down ordered arrays directly on amorphous dielectric surfaces to address the particle placement challenge. This process exploits the kinetic differences in two different materials systems, the etching rates of SiO₂ versus HfO₂ with Ge adatoms and of SiO₂ versus Si₃N₄ with Si adatoms. A hard, sacrificial mask of SiO₂ is formed by etching through ~10 nm of SiO₂ to the underlying film of HfO₂ or Si₃N₄. The patterned SiO₂ serves as a sacrificial template during hot wire chemical vapor deposition at 800 K for Ge and 973 K for Si. Because Ge (Si) etches SiO₂ faster than HfO₂ (Si₃N₄), it is possible to accumulate Ge (Si) adatoms on HfO₂ (Si₃N₄) whereas the Ge (Si) adatom concentration on SiO₂ is too low for nucleation and growth. Adatom accumulation ultimately leads to nucleation of nanoparticles only on the exposed HfO₂ (or Si₃N₄) surfaces, thus the kinetics of the surface reactions control the bottom-up assembly processes. Top-down features are defined using the self assembly of a poly(styrene-b-methyl methacrylate) [P(S-b-MMA)] diblock copolymer on the SiO₂ mask layer to obtain features as small as 20 nm and up to 40 nm. E-beam lithography is also used for features of 100 nm and larger. The P(S-b-MMA) can organize into poly(methyl methacrylate) cylinders that are perpendicular with a silicon dioxide surface. These polymer films afford ideal masks since order is achievable across the majority of a substrate and the minority phase cylinders are selectively removed, leaving a polystyrene template robust enough to survive reactive ion etching and wet etching. We achieve long range ordered arrays of nanoparticles within 20 nm diameter cylinders with a 40 nm center-to-center spacing between cylinders. By varying the temperature, which controls the etching rate, and the flux of Si or Ge to the surface, we explore the kinetics of nanoparticle nucleation and growth at single nucleation sites.